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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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0d9c850a0713e3ff59a9ff2ab89e9fd47fd8aa08
yosys/techlibs
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Clifford Wolf 2a681909df Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
..
achronix
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
anlogic
Leave only real black box cells
2018-12-02 11:57:50 +01:00
common
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
coolrunner2
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
easic
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ecp5
ecp5: Add 'fake' DCU parameters
2018-11-09 18:25:42 +00:00
gowin
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
greenpak4
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ice40
Merge pull request #724 from whitequark/equiv_opt
2018-12-16 15:54:26 +01:00
intel
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
sf2
Fix sf2 LUT interface
2018-10-31 15:36:53 +01:00
xilinx
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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