Eddie Hung 0d7ba77426 Move \init from source wire to submod if output port		2019-11-25 16:07:47 -08:00
..
Makefile.inc	Rename "singleton" pass to "uniquify"	2017-08-20 12:31:50 +02:00
hierarchy.cc	Adopt @cliffordwolf's suggestion	2019-09-03 12:18:50 -07:00
submod.cc	Move \init from source wire to submod if output port	2019-11-25 16:07:47 -08:00
uniquify.cc	Add "whitebox" attribute, add "read_verilog -wb"	2019-04-18 17:45:47 +02:00