yosys/techlibs at 0d037bf9d8d866239de15d72dc8c5acd7ab5e5cf - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00

Files

T

History

David Shah e1d4e683b4 ecp5: Add ECLKBRIDGECS blackbox

Signed-off-by: David Shah <[email protected]>

2019-10-11 14:50:33 +01:00

..

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

make note that it is for latch mode

2019-09-18 17:48:16 +02:00

Missing (* mul2dsp *) for sliceB

2019-09-27 14:21:47 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5: Add ECLKBRIDGECS blackbox

2019-10-11 14:50:33 +01:00

better handling of lut and begin/end add

2019-09-18 17:45:07 +02:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Rename abc_* names/attributes to more precisely be abc9_*

2019-10-04 11:04:10 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Add link to SF2 / igloo2 macro library guide

2019-03-07 09:08:26 -08:00

xilinx: Add simulation model for IBUFG.

2019-10-10 13:16:03 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00