Eddie Hung 6464dc35ec Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd ...

xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder

2019-11-27 08:00:22 -08:00

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cmds

Add "autoname" pass and use it in "synth_ice40"

2019-11-13 13:41:16 +01:00

equiv

Add -async2sync to help text as per @daveshah1

2019-10-04 10:17:46 -07:00

fsm

Update fsm_detect bugfix

2019-11-12 17:31:30 +01:00

hierarchy

Adopt @cliffordwolf's suggestion

2019-09-03 12:18:50 -07:00

memory

Merge pull request #1501 from YosysHQ/dave/mem_copy_attr

2019-11-27 11:25:23 +01:00

opt

opt_share: Fix handling of fine cells.

2019-11-27 08:01:07 +01:00

pmgen

Check for either sign or zero extension for postAdd packing

2019-11-26 22:51:00 -08:00

proc

proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage

2019-11-21 20:46:41 +00:00

sat

Revert "Be mindful that sigmap(wire) could have dupes when checking \init"

2019-10-08 12:41:24 -07:00

techmap

clkbufmap: Add support for inverters in clock path.

2019-11-25 20:40:39 +01:00

tests

Document (* gentb_skip *) attr for test_autotb

2019-09-18 12:41:35 -07:00