yosys/tests/lut at 0ce1cbcae7af1902b421ff0acd0e00a8e8ba9de8 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00

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Miodrag Milanovic 9f75ca1f98 Release version 0.69

2026-09-09 07:26:44 +02:00

..

check_map_lut6.ys

Forgot to commit

2019-07-16 12:44:26 -07:00

check_map.ys

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

generate_mk.py

Adding test to demonstrate techmap failure with lut_cmp

2026-08-14 10:08:40 -06:00

lut.sh

Release version 0.69

2026-09-09 07:26:44 +02:00

map_and.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_cmp.v

Adding test to demonstrate techmap failure with lut_cmp

2026-08-14 10:08:40 -06:00

map_mux.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_not.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_or.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

map_xor.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00