mirror of https://github.com/YosysHQ/yosys.git
141 lines
3.6 KiB
Verilog
141 lines
3.6 KiB
Verilog
/* Generated by Preqorsor 0.45+139 (git sha1 2c3d2b3ec, c++ 15.0.0 -fPIC -O3) */
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(* \library = "work" *)
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(* hdlname = "top" *)
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(* src = "case.sv:1.8-1.11" *)
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module gate(clk, o, currentstate);
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wire _00_;
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wire _01_;
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wire _02_;
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wire _03_;
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wire _04_;
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wire _05_;
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wire _06_;
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wire _07_;
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wire _08_;
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wire _09_;
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wire _10_;
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(* src = "case.sv:2.8-2.11" *)
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input clk;
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wire clk;
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(* src = "case.sv:3.14-3.26" *)
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input [5:0] currentstate;
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wire [5:0] currentstate;
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(* src = "case.sv:4.19-4.20" *)
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output [1:0] o;
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reg [1:0] o;
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assign _02_ = | { _07_, _06_, _05_ };
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assign _03_ = | { _04_, _10_, _09_ };
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(* src = "case.sv:6.9-26.5" *)
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always @(posedge clk)
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o[1] <= _00_;
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(* src = "case.sv:6.9-26.5" *)
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always @(posedge clk)
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o[0] <= _01_;
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assign _04_ = currentstate == (* full_case = 32'd1 *) 3'h7;
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function [1:0] _16_;
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input [1:0] a;
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input [5:0] b;
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input [2:0] s;
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(* full_case = 32'd1 *)
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(* parallel_case *)
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casez (s)
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3'b??1:
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_16_ = b[1:0];
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3'b?1?:
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_16_ = b[3:2];
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3'b1??:
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_16_ = b[5:4];
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default:
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_16_ = a;
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endcase
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endfunction
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assign { _00_, _01_ } = _16_(2'h0, 6'h39, { _03_, _08_, _02_ });
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assign _05_ = currentstate == (* full_case = 32'd1 *) 1'h1;
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assign _06_ = currentstate == (* full_case = 32'd1 *) 2'h2;
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assign _07_ = currentstate == (* full_case = 32'd1 *) 2'h3;
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assign _08_ = currentstate == (* full_case = 32'd1 *) 3'h4;
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assign _09_ = currentstate == (* full_case = 32'd1 *) 3'h5;
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assign _10_ = currentstate == (* full_case = 32'd1 *) 3'h6;
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endmodule
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(* \library = "work" *)
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(* hdlname = "top" *)
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(* src = "case.sv:1.8-1.11" *)
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module gold(clk, o, currentstate);
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wire _00_;
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wire _01_;
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wire _02_;
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wire _03_;
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wire [1:0] _04_;
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wire _05_;
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wire _06_;
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wire _07_;
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wire _08_;
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wire _09_;
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(* src = "case.sv:2.8-2.11" *)
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input clk;
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wire clk;
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(* src = "case.sv:3.14-3.26" *)
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input [5:0] currentstate;
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wire [5:0] currentstate;
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(* src = "case.sv:4.19-4.20" *)
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output [1:0] o;
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reg [1:0] o;
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assign _01_ = currentstate == (* src = "case.sv:17.4-17.8" *) 3'h7;
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assign _05_ = currentstate == (* src = "case.sv:9.4-9.8" *) 1'h1;
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assign _06_ = currentstate == (* src = "case.sv:9.4-9.8" *) 2'h2;
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assign _07_ = currentstate == (* src = "case.sv:9.4-9.8" *) 2'h3;
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assign _08_ = currentstate == (* src = "case.sv:13.4-13.8" *) 3'h4;
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assign _09_ = currentstate == (* src = "case.sv:17.4-17.8" *) 3'h5;
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assign _00_ = currentstate == (* src = "case.sv:17.4-17.8" *) 3'h6;
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(* src = "case.sv:6.9-26.5" *)
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always @(posedge clk)
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o <= _04_;
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assign _02_ = | (* src = "case.sv:8.3-25.10" *) { _07_, _06_, _05_ };
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assign _03_ = | (* src = "case.sv:8.3-25.10" *) { _01_, _00_, _09_ };
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function [1:0] _20_;
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input [1:0] a;
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input [5:0] b;
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input [2:0] s;
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(* src = "case.sv:8.3-25.10" *)
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(* parallel_case *)
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casez (s)
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3'b??1:
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_20_ = b[1:0];
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3'b?1?:
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_20_ = b[3:2];
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3'b1??:
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_20_ = b[5:4];
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default:
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_20_ = a;
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endcase
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endfunction
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assign _04_ = _20_(2'h0, 6'h1b, { _02_, _08_, _03_ });
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endmodule
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module miter(in_clk, in_currentstate, trigger);
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wire _0_;
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wire [1:0] gate_o;
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wire [1:0] gold_o;
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input in_clk;
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wire in_clk;
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input [5:0] in_currentstate;
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wire [5:0] in_currentstate;
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output trigger;
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wire trigger;
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assign _0_ = gold_o === gate_o;
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always @* if (1'h1) assert(_0_);
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assign trigger = ~ _0_;
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gate gate (
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.clk(in_clk),
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.currentstate(in_currentstate),
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.o(gate_o)
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);
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gold gold (
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.clk(in_clk),
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.currentstate(in_currentstate),
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.o(gold_o)
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);
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endmodule
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