mirror of https://github.com/YosysHQ/yosys.git
d6bdefd2e9
* Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. |
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| .. | ||
| tests | ||
| .gitignore | ||
| Makefile.inc | ||
| arith_map.v | ||
| brams.txt | ||
| brams_bb.v | ||
| brams_init.py | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.sh | ||
| cells_xtra.v | ||
| drams.txt | ||
| drams_map.v | ||
| lut2lut.v | ||
| synth_xilinx.cc | ||