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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
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09467bb9a3ca01bb7bbfc6c9013ed7385e42fd96
yosys/backends
T
History
Clifford Wolf 1cd1b5fc1a Add "real" keyword to ilang format
Signed-off-by: Clifford Wolf <[email protected]>
2019-05-06 12:00:40 +02:00
..
aiger
Add "write_aiger -I -O -B"
2018-11-12 09:27:33 +01:00
blif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
btor
Change "ne" to "neq" in btor2 output
2019-04-19 21:17:12 +02:00
edif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
firrtl
Re-indent firrtl.cc:struct memory - no functional change.
2019-05-01 16:21:13 -07:00
ilang
Add "real" keyword to ilang format
2019-05-06 12:00:40 +02:00
intersynth
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
json
Revert "write_json to not write contents (cells/wires) of whiteboxes"
2019-04-18 23:05:59 -07:00
protobuf
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
smv
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
spice
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Improve write_verilog specify support
2019-05-04 08:46:24 +02:00
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