yosys/frontends/verilog
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
..
.gitignore
Makefile.inc
const2ast.cc Remove .c_str() calls from parameters to log_file_warning() 2025-09-16 23:03:45 +00:00
preproc.cc Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
preproc.h
verilog_error.cc
verilog_error.h
verilog_frontend.cc Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 2025-09-22 11:14:39 +02:00
verilog_frontend.h
verilog_lexer.h
verilog_lexer.l verilog: Bufnorm cell backend and frontend support 2025-09-17 14:01:09 +02:00
verilog_location.h
verilog_parser.y verilog_parser: replace manual AST node allocation with typed midrule actions 2025-09-13 11:23:42 +08:00