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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 20:36:44 +02:00
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08f85e64383c0248030873dcdcf388853d335eea
yosys/passes
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Eddie Hung 8119383f81 Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
..
cmds
Add "autoname" pass and use it in "synth_ice40"
2019-11-13 13:41:16 +01:00
equiv
Add -async2sync to help text as per @daveshah1
2019-10-04 10:17:46 -07:00
fsm
Update fsm_detect bugfix
2019-11-12 17:31:30 +01:00
hierarchy
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
memory
Add "opt_mem" pass
2019-11-22 17:45:22 +01:00
opt
Add "opt_mem" pass
2019-11-22 17:45:22 +01:00
pmgen
Fix #1462, #1480.
2019-11-19 08:57:39 +01:00
proc
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
2019-11-21 20:46:41 +00:00
sat
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
2019-10-08 12:41:24 -07:00
techmap
Fix #1496.
2019-11-18 04:16:48 +01:00
tests
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00
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