yosys/tests/arch at 07fb8af05baa2f47ebcbacfe8f036196ae8a8ba7 - yosys - Gitea: Git with a cup of tea

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Martin Povišer ca5c2fdff1 quicklogic: Relax the LUT number test

2024-10-07 15:27:03 +02:00

..

Update tests

2023-06-09 14:41:45 +02:00

Adding double_sync_ram_tdp to blockram.v

2023-12-04 15:52:03 +01:00

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous: Add support for mapping carry chains

2023-02-27 09:50:34 +01:00

Update tests

2023-06-09 14:41:45 +02:00

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

intel_alm: drop quartus support

2024-05-03 11:32:33 +01:00

put back previous test state, due to default change

2023-08-29 10:21:58 +02:00

inline all tests. Add switch to remove init values as PolarFire DFFs do not support init

2024-07-08 17:03:03 -04:00

add min_ce_use and min_srst_use parameters

2024-08-15 17:50:36 +02:00

Update tests

2023-06-09 14:41:45 +02:00

quicklogic: Relax the LUT number test

2024-10-07 15:27:03 +02:00

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

run-test.sh

Enable SV for localparam use by Efinix cell_sim

2024-04-08 12:45:43 +02:00