mirror of https://github.com/YosysHQ/yosys.git
222 lines
3.7 KiB
Plaintext
222 lines
3.7 KiB
Plaintext
log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s,
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output wire x
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);
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assign x = s ? 1'b0 : a;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$not
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design -reset
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log -pop
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log -header "Case with inverted a"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s,
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output wire x
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);
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assign x = s ? 1'b0 : ~a;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 2 t:$not
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design -reset
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log -pop
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log -header "Case with inverted s"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s,
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output wire x
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);
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assign x = ~s ? a : 1'b0;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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# Did not include check for not count since we have an unassigned ~s wire
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design -load postopt
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select -assert-count 1 t:$and
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design -reset
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log -pop
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log -header "Nested AND gates"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire s,
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output wire x
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);
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assign x = s ? 1'b0 : a & b;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$not
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design -reset
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log -pop
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log -header "Nested OR gates"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire s,
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output wire x
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);
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assign x = s ? 1'b0 : a | b;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$not
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "Nested muxes"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s1,
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input wire s2,
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output wire x
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);
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assign x = s1 ? 1'b0 : (s2 ? 1'b0 : a);
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 2 t:$not
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design -reset
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log -pop
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log -header "With constant propagation"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s,
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output wire x
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);
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assign x = s ? 1'b0 : a & 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$not
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design -reset
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log -pop
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log -header "With multibit constant"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire s,
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output wire x
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);
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assign x = s ? 32'b0 : a;
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endmodule
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EOF
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check -assert
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# Runs wreduce to reduce width of the constant before applying opt_expr
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# Without this line, this test case will not pass
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# Believe it is intended behavior to not optimize constant with more than one bit
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wreduce
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# Check equivalence after opt_expr
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equiv_opt -assert opt_expr -mux_bool
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$not
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design -reset
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log -pop |