mirror of https://github.com/YosysHQ/yosys.git
10 lines
554 B
Plaintext
10 lines
554 B
Plaintext
read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map prims.v synth_fabulous -carry ha -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-max 10 t:LUT4_HA
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select -assert-max 4 t:LUT1
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select -assert-none t:LUT1 t:LUT4_HA %% t:* %D
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