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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 03:32:09 +02:00
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0642baabbceaf4e34ae03c47136ed987b976cdbb
yosys/techlibs/ecp5
T
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Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
..
.gitignore
ecp5: First BRAM type maps successfully
2018-10-10 16:35:19 +01:00
arith_map.v
ecp5: Increase threshold for ALU mapping
2019-01-21 12:33:47 +00:00
bram.txt
ecp5: First BRAM type maps successfully
2018-10-10 16:35:19 +01:00
brams_connect.py
ecp5: Script for BRAM IO connections
2018-10-10 16:11:00 +01:00
brams_init.py
ecp5: First BRAM type maps successfully
2018-10-10 16:35:19 +01:00
brams_map.v
ecp5: Disable LSR inversion
2018-10-16 12:48:39 +01:00
cells_bb.v
ecp5: Add DDRDLLA
2019-02-19 19:34:37 +00:00
cells_map.v
ecp5: Compatibility with Migen AsyncResetSynchronizer
2019-02-25 13:24:30 +00:00
cells_sim.v
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
dram.txt
ecp5: Don't map ROMs to DRAM
2018-10-01 18:34:41 +01:00
drams_map.v
ecp5: Adding DRAM map
2018-07-13 14:08:42 +02:00
ecp5_ffinit.cc
ecp5: Demote conflicting FF init values to a warning
2019-03-04 11:26:20 +00:00
latches_map.v
ecp5: Add latch inference
2018-10-19 15:16:40 +01:00
Makefile.inc
ecp5: Support for flipflop initialisation
2019-01-22 16:02:56 +00:00
synth_ecp5.cc
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
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