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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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0642baabbceaf4e34ae03c47136ed987b976cdbb
yosys/techlibs/anlogic
T
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Eddie Hung 9a6da9a79a synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
..
anlogic_determine_init.cc
anlogic: implement DRAM initialization
2018-12-20 07:56:15 +08:00
anlogic_eqn.cc
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
arith_map.v
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
cells_map.v
Merge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 15:52:22 +01:00
cells_sim.v
Fixed Anlogic simulation model
2019-01-25 19:25:25 +01:00
dram_init_16x4.vh
anlogic: implement DRAM initialization
2018-12-20 07:56:15 +08:00
drams_map.v
anlogic: implement DRAM initialization
2018-12-20 07:56:15 +08:00
drams.txt
anlogic: implement DRAM initialization
2018-12-20 07:56:15 +08:00
eagle_bb.v
Revert "Leave only real black box cells"
2018-12-17 23:20:40 +08:00
Makefile.inc
anlogic: implement DRAM initialization
2018-12-20 07:56:15 +08:00
synth_anlogic.cc
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
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