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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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056c12eb6ffcb0c0c24e9fa5b994292bec18b187
yosys/frontends
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Kamil Rakoczy 61501e3266 Fix input/output attributes when resolving typedef of wire
Signed-off-by: Kamil Rakoczy <[email protected]>
2021-01-18 17:31:22 +01:00
..
aiger
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
ast
Fix input/output attributes when resolving typedef of wire
2021-01-18 17:31:22 +01:00
blif
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
json
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
liberty
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
rpc
Fix argument handling in connect_rpc
2020-10-19 13:40:57 +02:00
rtlil
rtlil: remove dotted identifiers.
2020-11-25 16:47:20 +00:00
verific
Bump required Verific version
2020-12-02 15:18:04 +01:00
verilog
Parse package user type in module port list
2021-01-18 17:31:22 +01:00
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