Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 20:47:34 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
043f1e2bcba3d3ee447ffbf5b2caefd706b7374d
yosys/passes
T
History
Martin Povišer 043f1e2bcb opt_lut: Remove leftover -dlogic help
2024-02-08 17:49:44 +01:00
..
cmds
Merge pull request #4174 from YosysHQ/claire/overwrite
2024-02-05 23:49:24 +01:00
equiv
equiv_simple: Fix seed handling in non-short mode
2023-10-03 13:05:42 +02:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 10:31:40 +01:00
memory
Fix printf formats
2024-01-15 12:07:54 +01:00
opt
opt_lut: Remove leftover -dlogic help
2024-02-08 17:49:44 +01:00
pmgen
peepopt: handle empty src-attribute in shiftadd
2024-01-31 13:07:01 +01:00
proc
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
sat
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
techmap
booth: Redo baseline architecture summation
2023-11-22 15:47:11 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
Powered by Gitea Version: 1.27.2 Page: 869ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API