yosys/passes
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells.
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
2026-01-06 16:21:48 +00:00
..
cmds Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 2026-01-06 16:21:48 +00:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap Switch posix_spawn to posix_spawnp 2025-12-15 09:40:04 +13:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00