yosys

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T

Catherine cb07710162 write_verilog: only warn on processes with sync rules.

Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.

This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.

2024-04-02 14:48:44 +01:00

aiger

write_aiger: Include $assert and $assume cells in -ywmap output

2024-03-04 16:53:03 +01:00

blif

Ignore $scopeinfo in write_blif

2024-02-06 17:51:29 +01:00

btor

tests: use /usr/bin/env for bash.

2023-08-12 11:59:39 +10:00

cxxrtl

fmt: if enabled, group padding zeroes.