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tests
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…
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.gitignore
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…
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Makefile.inc
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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2020-05-14 10:33:56 -07:00 |
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abc9_model.v
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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2020-05-14 10:33:56 -07:00 |
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arith_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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brams_init.py
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…
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cells_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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cells_sim.v
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xilinx: tidy up cells_sim.v a little
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2020-05-25 09:48:11 -07:00 |
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cells_xtra.py
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xilinx: Mark IOBUFDS.IOB as external pad
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2020-03-20 14:37:38 +01:00 |
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cells_xtra.v
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xilinx: Mark IOBUFDS.IOB as external pad
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2020-03-20 14:37:38 +01:00 |
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lut4_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut6_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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lutrams_map.v
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…
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mux_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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synth_xilinx.cc
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xilinx/ice40/ecp5: zinit requires selected wires, so select them all
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2020-05-14 10:33:56 -07:00 |
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xc2v_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc2v_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3s_mult_map.v
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…
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xc3sa_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_dsp_map.v
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…
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xc4v_dsp_map.v
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…
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xc5v_dsp_map.v
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…
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xc6s_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_dsp_map.v
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…
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xc6s_ff_map.v
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…
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xc7_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc7_dsp_map.v
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…
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xc7_ff_map.v
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…
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xc7_xcu_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_dsp_map.v
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…
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xcup_urams.txt
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…
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xcup_urams_map.v
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…
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xilinx_dffopt.cc
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xilinx: improve xilinx_dffopt message
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2020-04-22 16:25:23 -07:00 |
5b81df57c8