yosys/techlibs/intel at 02ba85b13302f0d20f6b51cc7fdff2fb953421df - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 18:01:44 +02:00

Files

T

History

Ben Widawsky 05d8cc4567 Fix formatting for synth_intel.cc

This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <[email protected]>

2019-05-09 08:40:05 -07:00

..

Clean whitespace and permissions in techlibs/intel

2017-10-05 16:23:49 +02:00

Changes in GoWin synth commands and ALU primitive support

2018-12-03 20:08:35 -06:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Fixing issues in CycloneV cell sim

2019-04-11 19:59:03 -05:00

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Makefile.inc

Initial Cyclone 10 support

2017-11-08 22:45:21 -06:00

synth_intel.cc

Fix formatting for synth_intel.cc

2019-05-09 08:40:05 -07:00