Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings

2020-07-23 11:57:07 +01:00

..

abc9_map.v

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abc9_model.v

intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF

2020-07-04 19:45:10 +02:00

abc9_unmap.v

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alm_map.v

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alm_sim.v

intel_alm: add additional ABC9 timings

2020-07-23 11:57:07 +01:00

arith_alm_map.v

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bram_m10k_map.v

Revert "intel_alm: direct M10K instantiation"

2020-07-13 18:05:38 +02:00

bram_m10k.txt

Revert "intel_alm: direct M10K instantiation"

2020-07-13 18:05:38 +02:00

bram_m20k_map.v

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bram_m20k.txt

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dff_map.v

synth_intel_alm: Use dfflegalize.

2020-07-04 22:56:16 +02:00

dff_sim.v

intel_alm: add additional ABC9 timings

2020-07-23 11:57:07 +01:00

dsp_map.v

intel_alm: DSP inference

2020-07-05 05:39:20 +02:00

dsp_sim.v

intel_alm: add additional ABC9 timings

2020-07-23 11:57:07 +01:00

lutram_mlab.txt

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megafunction_bb.v

Revert "intel_alm: direct M10K instantiation"

2020-07-13 18:05:38 +02:00

mem_sim.v

intel_alm: add additional ABC9 timings

2020-07-23 11:57:07 +01:00

quartus_rename.v

Revert "intel_alm: direct M10K instantiation"

2020-07-13 18:05:38 +02:00