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luke/yosys
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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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01f8d50ba239e98de1e6a75aec314caeae297bc8
yosys/passes
T
History
Eddie Hung 2ca83005fb abc9 to cope with multiple modules
2019-02-20 12:56:15 -08:00
..
cmds
Switch "bugpoint" from system() to run_command()
2019-01-07 09:45:21 +01:00
equiv
Fix equiv_opt indenting
2018-12-16 15:57:28 +01:00
fsm
fsm_opt: Fix runtime error for FSMs without a reset state
2019-02-07 10:35:36 +00:00
hierarchy
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
memory
memory_collect: do not truncate 'x from \INIT.
2018-12-21 02:01:27 +00:00
opt
Bugfix in $memrd sharing
2019-01-07 10:04:47 +01:00
proc
proc_clean: fix critical typo.
2019-01-23 22:08:38 +00:00
sat
expose command to not skip 'internal' wires beginning with '$'
2019-02-16 13:45:17 -08:00
techmap
abc9 to cope with multiple modules
2019-02-20 12:56:15 -08:00
tests
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
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