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yosys/tests/svtypes
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Brett Witherspoon 979053855c sv: improve support for wire and var with user-defined types 
- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
2021-08-12 22:41:41 -06:00
..
.gitignore
…
enum_simple.sv
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
enum_simple.ys
…
logic_rom.sv
ast/simplify: don't bitblast async ROMs declared as logic.
2020-05-05 04:16:59 +00:00
logic_rom.ys
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
multirange_array.sv
Test multirange (unpacked) arrays size
2020-08-03 15:34:55 +02:00
multirange_subarray_access.ys
Add test for subarray access on multidimensional arrays
2020-08-03 17:07:33 +02:00
run-test.sh
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
static_cast_negative.ys
static cast: add tests
2020-06-19 17:40:38 -07:00
static_cast_nonconst.ys
static cast: add tests
2020-06-19 17:40:38 -07:00
static_cast_simple.sv
static cast: add tests
2020-06-19 17:40:38 -07:00
static_cast_verilog.ys
static cast: add tests
2020-06-19 17:40:38 -07:00
static_cast_zero.ys
static cast: add tests
2020-06-19 17:40:38 -07:00
struct_array.sv
include both power-of-two and non-power-of-two testcases
2020-08-18 18:54:22 +02:00
struct_simple.sv
Allow structs within structs.
2020-05-12 17:20:34 +01:00
typedef_initial_and_assign.sv
sv: improve support for wire and var with user-defined types
2021-08-12 22:41:41 -06:00
typedef_initial_and_assign.ys
sv: improve support for wire and var with user-defined types
2021-08-12 22:41:41 -06:00
typedef_memory_2.sv
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
typedef_memory_2.ys
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
typedef_memory.sv
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
typedef_memory.ys
Add v2 memory cells.
2021-08-11 13:34:10 +02:00
typedef_package.sv
support using previously declared types/localparams/params in package
2020-04-07 00:38:15 -04:00
typedef_param.sv
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
typedef_scopes.sv
verilog: check entire user type stack for type definition
2021-03-21 19:35:13 -04:00
typedef_simple.sv
Revert typedef tests to standard grammar.
2020-03-22 18:20:46 -07:00
typedef_struct_port.sv
Add typedef input/output test
2021-01-18 17:31:22 +01:00
typedef_struct_port.ys
Add typedef input/output test
2021-01-18 17:31:22 +01:00
typedef_struct.sv
Implement SV structs.
2020-05-08 14:40:49 +01:00
union_simple.sv
Allow structs within structs.
2020-05-12 17:20:34 +01:00