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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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0113f44faaa5778afd0fa3afbdbf12f33f2cea4e
yosys/tests/arch
T
History
Jannis Harder 0113f44faa Reenable existing equiv_opt tests
2022-10-07 16:04:51 +02:00
..
anlogic
anlogic: support BRAM mapping
2021-12-17 20:28:22 +08:00
common
Allow initial blocks to be disabled during tests
2021-11-13 21:53:25 +01:00
ecp5
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
efinix
efinix: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
gatemate
gatemate: Add test for LUT tree mapping
2022-06-27 10:09:48 +01:00
gowin
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
ice40
Reenable existing equiv_opt tests
2022-10-07 16:04:51 +02:00
intel_alm
Reenable existing equiv_opt tests
2022-10-07 16:04:51 +02:00
machxo2
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
nexus
nexus: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
quicklogic
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
xilinx
Fix tests for check in equiv_opt
2022-10-07 16:04:51 +02:00
run-test.sh
Add default assignments to SB_LUT4
2021-04-20 12:46:21 +02:00
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