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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00
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0113f44faaa5778afd0fa3afbdbf12f33f2cea4e
yosys/frontends/verilog
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Miodrag Milanovic b76c72056b set default_nettype to wire for resetall
2022-08-10 13:28:19 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
Makefile.inc
Treat all bison warnings as errors in verilog front-end
2020-07-15 11:57:31 +02:00
preproc.cc
set default_nettype to wire for resetall
2022-08-10 13:28:19 +02:00
preproc.h
verilog: save and restore overwritten macro arguments
2021-07-28 21:52:16 -04:00
verilog_frontend.cc
verilog: Squash a memory leak.
2021-06-14 17:07:41 +02:00
verilog_frontend.h
verilog: Squash a memory leak.
2021-06-14 17:07:41 +02:00
verilog_lexer.l
verilog: support for time scale delay values
2022-02-14 15:58:31 +01:00
verilog_parser.y
verilog: support for time scale delay values
2022-02-14 15:58:31 +01:00
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