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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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2026-10-07 18:43:22 +02:00
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00f29d5e5cdd08a14aa02119f46f8ee10cd1368d
yosys
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frontends
T
History
Clifford Wolf
e9fe57c75e
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
..
ast
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
blif
Added "read_blif -sop"
2016-06-18 12:33:13 +02:00
ilang
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
liberty
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
verific
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
verilog
Fixed bug in parsing real constants
2016-08-06 13:16:23 +02:00
vhdl2verilog
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
