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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
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0070184ea9dea56d1dfd8268035bc01a3e340add
yosys/tests/various
T
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Clifford Wolf 0070184ea9 Improvements in pmux2shiftx
Signed-off-by: Clifford Wolf <[email protected]>
2019-04-20 00:38:25 +02:00
..
.gitignore
Added tests/various/.gitignore
2014-07-26 17:43:41 +02:00
constmsk_test.v
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_test.ys
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_testmap.v
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
hierarchy.sh
Address requested changes - don't require non-$ name.
2019-02-22 16:06:10 -08:00
muxcover.ys
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
2019-04-15 17:52:45 -07:00
pmux2shiftx.v
Improvements in pmux2shiftx
2019-04-20 00:38:25 +02:00
pmux2shiftx.ys
Improvements in pmux2shiftx
2019-04-20 00:38:25 +02:00
reg_wire_error.sv
Modified errors into warnings
2018-06-05 18:03:22 +03:00
reg_wire_error.ys
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
run-test.sh
Address requested changes - don't require non-$ name.
2019-02-22 16:06:10 -08:00
submod_extract.ys
Added tests/various/submod_extract.ys
2014-07-26 17:22:18 +02:00
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