Miodrag Milanovic acb341745d Fix invalid verilog syntax

2020-03-14 14:33:44 +01:00

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.gitignore

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abc9_model.v

Create +/abc9_model.v for $__ABC9_{DELAY,FF_}

2020-02-27 10:17:29 -08:00

adff2dff.v

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cellhelp.py

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cells.lib

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cmp2lut.v

Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp

2019-11-11 15:07:29 +01:00

dff2ff.v

Add dff2ff.v techmap file

2017-05-31 11:45:58 +02:00

gate2lut.v

Fix invalid verilog syntax

2020-03-14 14:33:44 +01:00

Makefile.inc

Create +/abc9_model.v for $__ABC9_{DELAY,FF_}

2020-02-27 10:17:29 -08:00

mul2dsp.v

Missing (* mul2dsp *) for sliceB

2019-09-27 14:21:47 -07:00

pmux2mux.v

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prep.cc

Add "wreduce -keepdc", fixes #1016

2019-05-20 15:36:13 +02:00

simcells.v

Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

2019-08-06 04:47:55 +02:00

simlib.v

Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

2019-08-09 12:33:39 -07:00

synth.cc

Add -flowmap to synth and synth_ice40

2020-02-28 14:29:57 +00:00

techmap.v

techmap: fix shiftx2mux decomposition

2020-02-07 11:02:48 -08:00