mirror of https://github.com/YosysHQ/yosys.git
32 lines
640 B
Plaintext
32 lines
640 B
Plaintext
read_verilog <<EOT
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module top(input d, en, output reg q);
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always @* if (en) q = d;
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endmodule
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EOT
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design -save read
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logger -expect warning "Latch inferred for signal" 1
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synth_ice40 -latches warn
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logger -check-expected
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select -assert-count 1 t:SB_LUT4
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design -load read
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synth_ice40 -latches info
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select -assert-count 1 t:SB_LUT4
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# always_latch
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design -reset
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read_verilog -sv <<EOT
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module top(input d, en, output reg q);
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always_latch if (en) q = d;
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endmodule
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EOT
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logger -expect-no-warnings
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synth_ice40
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logger -check-expected
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select -assert-count 1 t:SB_LUT4
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design -load read
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logger -expect error "Latch inferred for signal" 1
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synth_ice40
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