luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
yosys/tests/errors/syntax_err01.v

4 lines
37 B
Verilog
Raw Permalink Blame History

module a;
integer [31:0]w;
endmodule
Reference in New Issue View Git Blame Copy Permalink