mirror of https://github.com/YosysHQ/yosys.git
40 lines
983 B
Plaintext
40 lines
983 B
Plaintext
read_verilog -specify boxes.v
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design -save read
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select -assert-none =a:test_attr
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select -assert-none =A:test_attr
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# setattr =* affects all modules
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setattr -set test_attr 1 =*
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select -assert-mod-count 3 =a:test_attr
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select -assert-none =A:test_attr
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design -load read
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setattr -mod -set test_attr 1 =*
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select -assert-none =a:test_attr
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select -assert-mod-count 3 =A:test_attr
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# setattr * doesn't affect boxed modules
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design -load read
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setattr -mod -set test_attr 1 *
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select -assert-mod-count 1 =A:test_attr
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# setattr can set and unset whitebox attr
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design -load read
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setattr -mod -unset whitebox =wb
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select -assert-mod-count 2 *
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setattr -mod -set whitebox 1 wb
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select -assert-mod-count 1 *
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# wbflip works on all non-bb in selection
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design -load read
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select -assert-mod-count 1 =A:whitebox
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wbflip
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select -assert-mod-count 2 =A:whitebox
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wbflip
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select -assert-mod-count 2 =A:whitebox
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wbflip =wb
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select -assert-mod-count 1 =A:whitebox
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wbflip =bb
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select -assert-mod-count 1 =A:whitebox
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