mirror of https://github.com/YosysHQ/yosys.git
30 lines
668 B
Plaintext
30 lines
668 B
Plaintext
read_verilog -specify boxes.v
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design -save read
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logger -expect-no-warnings
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delete =bb %n
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select -assert-mod-count 1 =*
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design -stash just_bb
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design -import just_bb
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select -assert-mod-count 0 *
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select -assert-mod-count 1 =*
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design -reset
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design -import just_bb -as new
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select -assert-mod-count 0 *
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select -assert-mod-count 1 =*
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design -reset
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design -import read -as new_top top
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design -import read -as new_bb =bb
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select -assert-mod-count 1 *
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select -assert-mod-count 2 =*
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logger -check-expected
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logger -expect warning "Selection .wb. did not match any module\." 1
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logger -expect error "No top module found in source design\." 1
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design -import read -as new_wb wb
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