mirror of https://github.com/YosysHQ/yosys.git
18 lines
386 B
Plaintext
18 lines
386 B
Plaintext
read_verilog -sv -formal <<EOF
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module counter(input clk, input [2:0] rst, input [0:3] rst_val, output logic is_full);
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logic [1:0] ctr;
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always @(posedge clk)
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if (rst)
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ctr <= 0;
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else
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ctr <= ctr+1;
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assign is_full = (ctr == 2'b11);
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endmodule
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EOF
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hierarchy -check -top counter
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prep -top counter
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fminit -seq rst 0,1,2'b11,2'sb11,rst_val
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