mirror of https://github.com/YosysHQ/yosys.git
58 lines
1.1 KiB
Plaintext
58 lines
1.1 KiB
Plaintext
read_verilog -sv << EOF
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module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
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always @* begin
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W = F;
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(* full_case *)
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case (C)
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A: W = D;
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B: W = E;
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endcase
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end
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always @* begin
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X = F;
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case (C)
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A: X = D;
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B: X = E;
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endcase
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end
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always @* begin
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Y = F;
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(* full_case, parallel_case *)
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case (C)
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A: Y = D;
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B: Y = E;
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endcase
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end
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always @* begin
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Z = F;
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(* parallel_case *)
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case (C)
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A: Z = D;
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B: Z = E;
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endcase
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end
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endmodule
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EOF
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prep
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# For the ones which use full_case, the F signal shouldn't be included in
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# the input cone of W and Y.
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select -set full o:W o:Y %u %ci*
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select -assert-none i:F @full %i
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select -assert-count 1 o:X %ci* i:F %i
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select -assert-count 1 o:Z %ci* i:F %i
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# And for parallel_case there should be 1 $pmux compared to the 2 $mux
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# cells without.
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select -assert-none o:W %ci* t:$pmux %i
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select -assert-none o:X %ci* t:$pmux %i
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select -assert-count 1 o:Y %ci* t:$pmux %i
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select -assert-count 1 o:Z %ci* t:$pmux %i
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select -assert-count 2 o:W %ci* t:$mux %i
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select -assert-count 2 o:X %ci* t:$mux %i
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select -assert-none o:Y %ci* t:$mux %i
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select -assert-none o:Z %ci* t:$mux %i
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