mirror of https://github.com/YosysHQ/yosys.git
39 lines
568 B
Plaintext
39 lines
568 B
Plaintext
module \m_a
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wire input 1 \w_i
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wire output 2 \w_o
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connect \w_o \w_i
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end
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module \m_b
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wire input 1 \w_i
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wire output 2 \w_o
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end
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attribute \top 1
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module \top
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attribute \raise_error 3
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wire \w_a
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wire \w_b
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wire \w_c
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cell \m_a \c_a
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connect \w_i \w_a
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connect \w_o \w_b
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end
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cell \m_a \c_b
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connect \w_i \w_b
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connect \w_o \w_c
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end
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cell \m_b \c_c
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connect \w_i \w_c
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connect \w_o \w_a
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end
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cell \m_b \c_d
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connect \w_i 1'0
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connect \w_o 1'1
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end
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end
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