mirror of https://github.com/YosysHQ/yosys.git
d60dc93e92
The dynamic clock selection (DCS) primitive has undergone changes with the release of the GW5A series—the CLK0,1,2,3 inputs are now CLKIN0,1,2,3, but only for GW5A series chips. There are no functional changes, only renaming. Here we are transferring the description of the DCS primitive from general to specialized files for each chip series. We have also fixed a bug in the generation script that caused the loss of primitive parameters. Fortunately, this only affected the analog-to-digital converter, which has not yet been implemented. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| Makefile.inc | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra_gw1n.v | ||
| cells_xtra_gw2a.v | ||
| cells_xtra_gw5a.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| synth_gowin.cc | ||