mirror of https://github.com/YosysHQ/yosys.git
18 lines
411 B
Plaintext
18 lines
411 B
Plaintext
module \gold
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wire input 1 \clk
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wire input 1 \wen
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wire input 3 \addr
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wire input 4 \wdata
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wire input 4 \rdata
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cell $__MEMORY \m
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parameter \WIDTH 4
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parameter \ABITS 3
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parameter \INIT 32'11011110101011011011111011101111
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connect \PORT_A_CLK \clk
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connect \PORT_A_ADDR \addr
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connect \PORT_A_WR_DATA \wdata
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connect \PORT_A_WR_EN \wen
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connect \PORT_A_RD_DATA \rdata
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end
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end
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