mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-08 04:41:06 +02:00
9 lines
127 B
Verilog
9 lines
127 B
Verilog
module bus_con (a,b, y);
|
|
input [3:0] a, b;
|
|
output [7:0] y;
|
|
wire [7:0] y;
|
|
|
|
assign y = {a,b};
|
|
|
|
endmodule
|