Files
2026-06-23 07:23:41 +02:00
..
2026-06-23 07:23:41 +02:00
2026-06-23 07:23:41 +02:00
2026-06-23 07:23:41 +02:00
2026-06-23 07:23:41 +02:00
2017-04-12 15:11:09 +02:00
2015-10-13 15:41:20 +02:00
2026-06-23 07:23:41 +02:00
2026-06-23 07:23:41 +02:00
2026-06-23 07:23:41 +02:00

In this directory contains an example for generating a spice output using two
different spice modes, normal analog transient simulation and event-driven
digital simulation as supported by ngspice xspice sub-module.

Each test bench can be run separately by either running:

- testbench.sh, to start analog simulation or
- testbench_digital.sh for mixed-signal digital simulation.

The later case also includes pure verilog simulation using the iverilog
and gtkwave for comparison.