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11 lines
212 B
Verilog
11 lines
212 B
Verilog
module dlatchsr_mixedpol(input ENA, D, CLEAR, PRESET, output reg Q, output QN);
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always @*
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if (PRESET) Q <= 1'b1;
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else if (~CLEAR) Q <= 1'b0;
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else if (ENA) Q <= ~D;
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assign QN = ~Q;
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endmodule
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