mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-09-06 11:59:46 +02:00
9 lines
132 B
Systemverilog
9 lines
132 B
Systemverilog
module top;
|
|
rand const reg rx;
|
|
const reg ry;
|
|
rand reg rz;
|
|
rand const integer ix;
|
|
const integer iy;
|
|
rand integer iz;
|
|
endmodule
|