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12 lines
179 B
Systemverilog
12 lines
179 B
Systemverilog
module local_loop_top(out);
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output integer out;
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initial begin
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integer i;
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for (i = 0; i < 5; i = i + 1)
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if (i == 0)
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out = 1;
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else
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out += 2 ** i;
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end
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endmodule
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