Files
yosys/tests/pyosys/test_indirect_inheritance.py
2026-08-13 18:15:58 +02:00

16 lines
363 B
Python

from pyosys import libyosys as ys
from pathlib import Path
__file_dir__ = Path(__file__).absolute().parent
d = ys.Design()
ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
ys.run_pass("hierarchy -top spm", d)
for idstr, cell in d.top_module().cells_.items():
cell.set_bool_attribute(d.id_add("\\set"))
print(cell.attributes)
break