nella f5809a7c2c Merge branch 'main' into nella/latch-toggle

2026-07-08 11:41:08 +02:00

..

.gitignore

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

add_sub.ys

End of file fix

2026-06-23 07:23:41 +02:00

adffs.ys

Share common tests

2019-10-18 12:19:59 +02:00

bug1597.ys

Reenable existing equiv_opt tests

2022-10-07 16:04:51 +02:00

bug1598.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

bug1626.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

bug1644.il.gz

Add #1644 testcase

2020-01-17 15:57:52 -08:00

bug1644.ys

Remove references to ilang

2024-11-05 12:36:31 +13:00

bug2061.ys

opt_lut: Allow more than one -dlogic per cell type.

2021-07-29 17:30:07 +02:00

counter.ys

Call equiv_opt with -multiclock and -assert

2019-12-31 18:39:32 -08:00

dffs.ys

End of file fix

2026-06-23 07:23:41 +02:00

dpram.v

Moved all tests in arch sub directory

2019-10-18 11:06:12 +02:00

dpram.ys

Moved all tests in arch sub directory

2019-10-18 11:06:12 +02:00

fsm.ys

abc9: preserve topological-loop asserts with targeted SCC fallback

2026-02-26 22:30:32 -08:00

generate_mk.py

Convert gen-tests shell script to python

2026-04-16 11:00:44 +02:00

ice40_dsp_const.ys

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ice40_dsp.ys

test: ice40_dsp test to read +/ice40/cells_sim.v for default params

2020-04-22 16:35:35 -07:00

ice40_opt.ys

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

ice40_wrapcarry.ys

Change attribute search value to specify precise location instead of simple line number.

2020-02-24 02:41:08 +00:00

latches.ys

Fixup level policy.

2026-06-18 18:00:51 +02:00

logic.ys

Share common tests

2019-10-18 12:19:59 +02:00

macc.v

Moved all tests in arch sub directory

2019-10-18 11:06:12 +02:00

macc.ys

Moved all tests in arch sub directory

2019-10-18 11:06:12 +02:00

memories.ys

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

mul.ys

Fix warnings

2019-12-31 18:40:11 -08:00

mux.ys

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

rom.v

Revert insertion of 'reg', leave note behind

2020-01-01 09:05:46 -08:00

rom.ys

Update tests

2023-06-09 14:41:45 +02:00

shifter.ys

Share common tests

2019-10-18 12:19:59 +02:00

spram.v

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

spram.ys

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

tribuf.ys

Share common tests

2019-10-18 12:19:59 +02:00