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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 11:35:20 +02:00
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emil/srcref
yosys/techlibs/sf2
T
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Miodrag Milanovic a689342207 Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
..
tests
sf2: add a test for $alu gate
2022-08-31 08:40:44 +02:00
arith_map.v
End of file fix
2026-06-23 07:23:41 +02:00
cells_map.v
…
cells_sim.v
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
CMakeLists.txt
Migrate build system to CMake
2026-06-03 08:58:10 +00:00
NOTES.txt
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
synth_sf2.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
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