yosys/techlibs/quicklogic at emil/srcref - yosys - Gitea: Git with a cup of tea

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Emil J. Tywoniak b3c7a25be5 techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

CMakeLists.txt

Migrate build system to CMake

2026-06-03 08:58:10 +00:00

ql_bram_merge.cc

techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

ql_bram_types.cc

techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

ql_dsp_io_regs.cc

techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

ql_dsp_macc.cc

techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

techlibs: trivial twine damage

2026-08-13 18:15:58 +02:00

ql_ioff.cc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

synth_quicklogic.cc

Merge branch 'main' into nella/latch-toggle

2026-07-08 11:41:08 +02:00