yosys/tests/errors at emil/select-alias-cone - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00

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Miodrag Milanovic 48a3dcc02a End of file fix

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..

syntax_err01.v

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syntax_err02.v

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syntax_err03.v

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syntax_err04.v

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syntax_err05.v

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syntax_err06.v

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syntax_err07.v

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syntax_err08.v

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syntax_err09.v

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syntax_err10.v

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

syntax_err11.v

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

syntax_err12.v

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

syntax_err13.v

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2026-06-23 07:23:41 +02:00