Emil J. Tywoniak 19a4c29a0e Revert "intel: register bram celltypes" ... This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.		2026-05-22 18:40:16 +02:00
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common	Fixed data/address width parameters	2024-03-06 02:45:07 +01:00
cyclone10lp	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
cycloneiv	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
cycloneive	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
max10	Removed SystemVerilog module end label	2024-03-19 01:31:36 +01:00
Makefile.inc	synth_intel: Remove incomplete Arria 10 GX support.	2020-08-21 01:46:06 +02:00
synth_intel.cc	Revert "intel: register bram celltypes"	2026-05-22 18:40:16 +02:00