mirror of https://github.com/YosysHQ/yosys.git
98 lines
3.0 KiB
Plaintext
98 lines
3.0 KiB
Plaintext
read_verilog -icells <<EOT
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module top(input E, D, S, R, output [9:0] Q);
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$_DLATCH_P_ latch0 (.E(E), .D(D), .Q(Q[0]));
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$_DLATCH_PP0_ latch1 (.E(E), .D(D), .R(R), .Q(Q[1]));
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$_DLATCH_PP1_ latch2 (.E(E), .D(D), .R(R), .Q(Q[2]));
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$_DLATCHSR_PPP_ latch3 (.E(E), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DLATCHSR_NNN_ latch4 (.E(E), .D(D), .R(R), .S(S), .Q(Q[4]));
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assign Q[9:5] = ~Q[4:0];
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endmodule
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EOT
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simplemap
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design -save orig
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read_liberty -lib dlatchlibmap.lib
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equiv_opt -map dlatchlibmap-sim.v -assert -multiclock dfflibmap -liberty dlatchlibmap.lib
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equiv_opt -map dlatchlibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dlatchlibmap.lib
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dfflibmap -prepare -liberty dlatchlibmap.lib
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equiv_opt -map dlatchlibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dlatchlibmap.lib
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design -load orig
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dfflibmap -liberty dlatchlibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dlatchn
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select -assert-count 4 t:dlatchsr
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select -assert-none t:dlatchn t:dlatchsr t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dlatchlibmap.lib
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select -assert-count 9 t:$_NOT_
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select -assert-count 1 t:$_DLATCH_N_
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select -assert-count 4 t:$_DLATCHSR_PPP_
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select -assert-none t:$_DLATCH_N_ t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -map-only -liberty dlatchlibmap.lib
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select -assert-count 5 t:$_NOT_
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select -assert-count 0 t:dlatchn
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select -assert-count 1 t:dlatchsr
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select -assert-count 1 t:$_DLATCH_P_
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select -assert-count 1 t:$_DLATCH_PP0_
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select -assert-count 1 t:$_DLATCH_PP1_
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select -assert-count 1 t:$_DLATCHSR_NNN_
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design -load orig
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dfflibmap -prepare -liberty dlatchlibmap.lib
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dfflibmap -map-only -liberty dlatchlibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dlatchn
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select -assert-count 4 t:dlatchsr
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select -assert-none t:dlatchn t:dlatchsr t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dlatchlibmap_dlatchn.lib -liberty dlatchlibmap_dlatchsr_r.lib
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dfflibmap -map-only -liberty dlatchlibmap_dlatchn.lib -liberty dlatchlibmap_dlatchsr_r.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dlatchn
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select -assert-count 4 t:dlatchsr
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select -assert-none t:dlatchn t:dlatchsr t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -liberty dlatchlibmap.lib -dont_use *latchn
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clean
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select -assert-count 0 t:dlatchn
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select -assert-count 5 t:dlatchsr
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design -load orig
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dfflibmap -liberty dlatchlibmap.lib -liberty dlatchlibmap_dlatchsr_mixedpol.lib -dont_use dlatchsr
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clean
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# We have one more _NOT_ than with the regular dlatchsr
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select -assert-count 5 t:$_NOT_
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select -assert-count 1 t:dlatchn
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select -assert-count 4 t:dlatchsr_mixedpol
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# The additional NOT is on latch2.
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# Originally, latch2.R is an active high "preset".
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# dlatchsr_mixedpol has functionally swapped labels due to the data_in inversion,
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# so we use its CLEAR port for the "preset",
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# but we have to invert it because the CLEAR pin is active low.
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# latch2.CLEAR = !R
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select -assert-count 1 c:latch2 %x:+[CLEAR] %ci t:$_NOT_ %i
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